The subject system and method are generally directed to digital communications clock recovery. In particular, although not exclusively, a hybrid clock recovery system of analog and digital components adjusts the timing of a digital communications clock based on a phase error detected in an incoming signal.
When a data signal is sent from one device to another, it is important for the receiving device to have a clock signal properly synchronized with the data signal, so the boundary between each unit of data (e.g. a bit or a byte) in the data signal can be properly determined and the value of the unit thereby determined. If the receiving device clock signal is not synchronized with the data signal, the data signal value might be misread, as the receiving device is unsure when one unit of data is complete and the next has begun. At present speeds of data transmission, on the order of gigahertz, this clock signal must be accordingly precise, both generally and in the ability of the receiving device to synchronize it with the data signal.
The source device of a data signal may be plesiochronous with the receiving device, meaning that their clocks do not have exactly the same frequency and will slowly drift out of alignment. A data signal may also have “jitter” due to adjusting conditions, such as atmospheric or electromagnetic interference, “crosstalk,” or simple changes in distance between devices. Both these factors make synchronization an ongoing process.
The synchronizing process is generally handled by a circuit which delays either the data signal or the receiving device clock signal such that the “edges” of the two signals are re-aligned. To put it another way, the circuit determines a “phase” or “offset” of the data signal in comparison to the clock signal and applies the offset to the clock signal (or, in some systems, the timing of the data signal) to re-align the two.
However, present digital components have practical limits to the rate at which they can generate and apply the offset, particularly in response to the unpredictable effects of jitter. At the same time, analog components have their own limits. A more effective design, therefore, is desirable.